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Virtual Coffee with an Expert – ML in Embedded Systems

2020-09-16 @ 15:00 - 16:30


Synchoros VLSI Design Style: A Solution for Post Moore Era

Speaker: Ahmed Hemani

On September 16th, Prof. Ahmed Hemani will give a webinar about the topic of using lego as inspiration for hardware centric designs for ML and high-performance embedded systems that are power/battery limited.

Abstract: In post Moore era, we will need to efficiently create fully customized complex machines that exploits all available technology options to go beyond what Moore’s law has been enabling us with. This would include use of memristor based computation in memory, plasmonics, 3D DRAM vauts combined with conventional CMOS. Conventional standard cell based design flows will not suffice to deal with such diversity and complexity. We propose a new design style called synchoros VLSI design style to replace standard cells based VLSI design flows. Synchoricity, derived from the Greek word choros for space is the spatial analog of synchronicity. In synchronicity, we discretize time to enable temporal composition by abutment. In synchoricity, we discretize space to enable spatial composition by abutment. Synchoros VLSI design style has been used to design Lego like bricks called SiLago that replaces conventional standard cells as the atomic building blocks. SiLago blocks compose by abutment to create valid ready-to-manufacture designs without the end-user having to do logic and physical synthesis. We show, how synchoros SiLago based platform can automate custom hybrid designs to cope with both diversity of technologies and also deal with extreme complexity.

Bio: Ahmed Hemani is Professor in Electronic Systems Design at School of ICT, KTH, Kista, Sweden.  His current areas of research interests are massively parallel architectures and design methods and their applications to scientific computing and autonomous embedded systems inspired by brain. In past he has contributed to high-level synthesis – his doctoral thesis was the basis for the first high-level synthesis product introduced by Cadence called visual architect.  He has also pioneered the Networks-on-chip concept and has contributed to clocking and low power architectures and design methods.  He has extensively worked in industry including National Semiconductors, ABB, Ericsson, Philips Semiconductors, Newlogic. He has also been part of three start-ups.


This event will be held via Zoom. Register for the event below. A link to the meeting room will be sent out to attendees before the event starts.  


15:00 - 16:30


The ICES Network
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